15 Sep Silicon Logic Teams Up to Save Money
Big impact for video game makers
Eau Claire, WI– Silicon Logic Engineering has joined forces with Mentor Graphics of Wilsonville, Ore., to offer improved custom computer chip verification to customers all over the IT spectrum.
The business collaboration is meant to speed up design verification and reduce the risk of costly additional manufacturing operations due to undetected errors in very complex ASIC (application specific integrated circuit) designs.
This collaboration unites SLE’s design methodologies and Mentor’s popular VStation emulation environment. VStation, which simulates the chip’s functionality and performance within an electronic system, delivers 1,000 to 10,000 times performance increases over traditional software simulation approaches, the company says. SLE, which specializes in right first-time, high-end ASIC and SOC (system on chip) design services, has added VStation emulation solutions to its design process.
Jordan Selburn, principal analyst for research firm iSuppli, noted that chip verification has everything to do with cost of redoing the chips and time to market, especially for its single largest application area, the video game market.
“Can you imagine – well, you don’t have to imagine, I think it’s happened in the past – what happens if the roll-out for one of those gets pushed out by four months?” Selburn hypothesized. “They typically roll them out in July or August of some year. In September they hit the Christmas markets, and problems with one of these core pieces of silicon could just kill it. If it’s not on the shelf, [customers] can’t go for it.
“These are all sole-source parts because they’re custom,” Selburn added. “Nintendo or Microsoft can’t go to another supply source.”
Total time from start of design to getting some parts can be up to 18 months. Undetected chip functionality and performance errors often result in additional manufacturing cycles called “respins” that require new mask sets, which can cost $870,000 for 130nm designs and upwards of $1,500,000 for 90 nm designs, the companies noted in a release.
“The issue is, people spend a lot of time and money developing these custom or semi- custom chips; and the problem is, it doesn’t always work,” Selburn said. “And given the time it takes to do a design and given the time it takes to fix a design and the cost to do a design and the cost to fix a design, there’s a lot of importance on it getting done right from the start.”
With roots in the supercomputer industry, SLE specializes in detecting possible functionality and performance errors early in the ASIC design cycle. SLE has delivered more than 30 high-gate count, high-performance ASICs and system chips right-first-time to a variety of networking and computing systems customers. Mentor’s VStation emulation system is now an integral part of SLE’s complex ASIC design methodology that incorporates leading electronic design automation (EDA) products.
“We’ve been very impressed with the accuracy and performance of Mentor’s VStation and are currently adding VStation emulation services for our customers who are pushing the ASIC design envelope,” said Jeff West, president of SLE. “Adding Mentor’s VStation emulation to our design services offering furthers SLE’s ability to produce the ‘right-first-time’ ASIC designs that our customers expect.”
Lincoln Brunner is a Stevens Point, Wisconsin-based freelance writer and a regular contributor to the Wisconsin Technology Network. He can be reached at firstname.lastname@example.org.